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1 memory all data sheets are subject to change without notice (858) 503-3300- fax: (858) 503-3301- www.maxwell.com quad 8-bit multiplying cmos 8408 ?2002 maxwell technologies all rights reserved. d/a converter with memory 08.20.02 rev 1 f eatures : ?r ad -p ak ? patented shielding against natural ? space radiation ? total dose hardness: - equal to 100 krad (si), depending upon orbit and space mission ? package: - 28 pin r ad -p ak ? flat pack ? single supply ooperation (+5v) ? four 8 bit dacs in one 28 pin package ? d/as matched to within 1% ? ttl/cmos compatable ? four-quadrant multiplication d escription : maxwell technologies? 8408 is a monolithic quad 8-bit multi- plying digital-to-analog cmos c onverter. each dac has its own reference input, feedback resistor, and onboard data latches that feature read/write capability. the readback func- tion serves as memory for t hose systems requiring self-diag- nostics. a common 8-bit ttl/cmos compatible input port is used to load data into any of the four dac data-latches. control lines ds1 , ds2 and a/b determine which dac will accept data. data loading is similar to that of a rams write cycle. data can be read back onto the same bus with control line r/w . the 8408 is a bus compatible with most 8-bit microprocessors, including the 6800, 8080, 8085, and z80. the 8408 operates on a single +5 volt supply and dissipates less than 20 mw. the 8408 is manufactured using hi ghly stable, thin-film resis- tors on an advanced oxide-isolat ed, silicon-gate, cmos pro- cess. the improved latch-up resi stant design eliminates the need for external protec tive schottky diodes. maxwell technologies' patented r ad -p ak ? packaging technol- ogy incorporates radiation shie lding in the microcircuit pack- age. it eliminates the need for box shielding while providing the required radiation shielding fo r a lifetime in orbit or space mission. in a geo orbit, r ad -p ak provides greater than 100 krad (si) radiation dose toleranc e. this product is available with screening up to class s. logic diagram
memory 2 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 t able 1. 8408 p inout d escription p in s ymbol d escription 1v dd supply voltage 2v ref a ref voltage (a) 3r fb a ref feedback (a) 4i out 1a current output (1a) 5i out 2a /i out 2b current output (2a/2b) 6i out 1b current output (1b) 7r fb b ref feedback (b) 8v ref b ref voltage (b) 9 db0 (lsb) data bit 0, least significant bit 10 - 15 db 1 - 6 data bits 1-6 16 db 7 (msb) data bit 7, most significant bit 17 a/b a/b 18 r/w read/write 19 - 20 ds1 - 2 data strobes 21 v ref d ref voltage (d) 22 r fb d ref feedback (d) 23 i out 1d current output (1d) 24 i out 2c /i out 2d current output (2c/2d) 25 i out 1c current output (1c) 26 r fb c ref feedback (c) 27 v ref c ref voltage (c) 28 dgnd digital ground t able 2. 8408 a bsolute m aximum r atings p arameter s ymbol m in m ax u nit v dd to i out 2a, i out 2b, i out 2c, i out 2d -- 0 7 v v dd to dgnd -- 0 7 v i out 1a, i out 1b, i out 1c, i out 1d to dgnd -- -0.3 v dd + 0.3 v r rf a, r rf b, v rf c, r rf d to i out -- -- 25 v i out 2a, i out 2b, i out 2c, i out 2d to dgnd -- -0.3 v dd + 0.3 v db0 through db7 to dgnd -- -0.3 v dd + 0.3 v control logic input voltage to dgnd -- -0.3 v dd + 0.3 v v ref a, v ref b, v ref c, v ref d to i out 2a, i out 2b, i out 2c, i out 2d -- -- 25 v
memory 3 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 power dissipation p d -- 20 mw operating temperature t a -55 125 c storage temperature range t s -65 150 c t able 3. d elta l imits p arameter v ariation i dd 10% of value specified in table 4 t able 4. 8408 s pecifications (v dd = +5 v; v ref = 10v; v out a, b, c, d = 0v, t a = -55 to 125 c unless otherwise noted ) p arameter s ymbol t est c ondition s ubgroups m in t yp m ax u nit static accuracy resolution n 1, 2, 3 8 -- -- bits non-linearity 1, 2 inl 1, 2, 3 -- -- 1/2 lsb differential nonlinearity dnl 1, 2, 3 -- -- 1 lsb gain error g fse (using internal r fb ) 1, 2, 3 -- -- 1 lsb gain tempco 3, 4 tc gfs 1, 2, 3 -- 2 40 ppm/ c power supply rejection psr ? v dd = 10% 1, 2, 3 -- -- 0.001 %fsr/ % i out 1a, b,c, d leakage current 5 i lkg +25c 1 -- -- 30 na -55 to 125c 2, 3 -- -- 200 reference input input voltage range -- 1, 2, 3 -- -- 20 v input resistance r in 1, 2, 3 6 10 14 k ? digital inputs digital input high voltage v ih 1, 2, 3 2.4 -- -- v digital input low voltage v il 1, 2, 3 -- -- 0.8 v digital input current 6 i in +25c 1 -- 0.01 1.0 a -55 to 125c 2, 3 -- -- 10.0 digital input capacitance 4 c in 1, 2, 3 -- -- 8 pf data bus outputs digital output low v ol 16 ma sink 1, 2, 3 -- -- 0.4 v digital output high v oh 400 a source 1, 2, 3 4 -- -- v t able 2. 8408 a bsolute m aximum r atings p arameter s ymbol m in m ax u nit
memory 4 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 output leakage current i lkg +25c 1 -- 0.005 1.0 a -55 to 125c 2, 3 -- 0.075 10.0 dac outputs 4 propogation delay 7 t pd 9, 10, 11 -- 150 180 ns settling time 8, 9 t s 9, 10, 11 -- 190 250 ns output capacitance c out dac latches all ?0s? 9, 10, 11 -- -- 30 pf dac latches all ?1s? 9, 10, 11 -- -- 50 ac feedthrough ft 20 v p-p @ f = 100 khz 9, 10, 11 54 -- -- db switching characteristics 4, 10 write to data strobe time t ds1 +25c 9 90 -- -- ns t ds2 -55 to 125c 10, 11 145 -- -- data valid to strobe set-up time t dsu +25c 9 150 -- -- ns -55 to 125c 10, 11 175 -- -- data valid to strobe hold time t dh 9, 10, 11 10 -- -- ns dac select to strobe set-up time t as 9, 10, 11 0 -- -- ns dac select to strobe hold time t ah 9, 10, 11 0 -- -- ns write select to strobe set-up time t wsu 9, 10, 11 0 -- -- ns write select to strobe hold time t wh 9, 10, 11 0 -- -- ns read to data strobe width t rds +25c 9 220 -- -- ns -55 to 125c 10, 11 350 -- -- data strobe to output valid time t co +25c 9 320 -- -- ns -55 to 125c 10, 11 430 -- -- output data deselect time t otd +25c 9 200 -- -- ns -55 to 125c 10, 11 270 -- -- read select to strobe set-up time t rsu 9, 10, 11 0 -- -- ns read select to strobe hold time t rh 9, 10, 11 0 -- -- ns power supply voltage range v dd 1, 2, 31 4.5 -- 5.5 v supply current 11 i dd 1, 2, 3 -- -- 50 a supply current 12 i dd +25c 1 -- -- 1.0 ma -55 to 125c 2, 3 -- -- 1.5 t able 4. 8408 s pecifications (v dd = +5 v; v ref = 10v; v out a, b, c, d = 0v, t a = -55 to 125 c unless otherwise noted ) p arameter s ymbol t est c ondition s ubgroups m in t yp m ax u nit
memory 5 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 1. this is an end-point linearity specification. 2. guaranteed to be monotonic over t he full operating temperature range. 3. ppm/c of fsr (fsr = full scale range = v ref -1 lsb). 4. guaranteed by design. 5. all digital inputs = 0v; vref = +10v. 6. logic inputs are mos gates. typical input current at +25c is less than 10 na. 7. from digital input to 90% of final analog output current. 8. digital inputs = 0v to v dd or v dd to 0v. 9. extrapolated: ts (1/2 lsb) = tpd + 6.2 where = the measured first constant of the final rc decay. 10.see timing diagram 11. all digital inputs ?0? or v dd . 12.all digital inputs v ih or v il
memory 6 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f igure 1. t iming d iagram f igure 2. s upply c urrent vs . l ogic l evel
memory 7 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 circuit information the 8408 combines four identical 8-bit cmos dacs onto a single monolithic chip. ea ch dac has its own reference input, feedback resistor, and on-board data latches. it also features a read/write function that serves as an accessible memory location for digital-input data words. the dac?s three-state readback drivers place the data word back onto the data bus. d/a converter section each dac contains a highly stable, sili con-chromium, thin-film, r-2r resistor ladder network and eight pairs of current steering switches. these switches are in series with each ladder resistor and are single-pole, double-throw nmos transistors; the gates of these transistor s are controlled by cmos inverters. fi gure 3 shows a simplified circuit of the r-2r resistor ladder section, and figure 4 shows an approximate equivalent switch circuit. the current through each resistor leg is switched between iout 1 and iout 2. this maintains a constant current in each leg, regardless of the digital input logic states. each transistor switch has a finite ?o n? resistance that can introduce errors to the dac?s specified performance. these resistances must be acco unted for by making the voltage drop across each transistor equal to each other. this is done by binarily scaling the transistor?s ?on? resistance from the most significant bit (msb) to the least significant bit (lsb). with 10 volts applied at the reference input, the current through the msb switch is 0.5 ma, the next bit is 0.25 ma, etc.; this maintains a constant 10 mv drop across each switch and the converter?s accuracy is maintained. it also results in a constant resistance appearing at the dac?s reference input terminal; this allows the dac to be driven by a voltage or current source, ac or dc, of positive or negative polarity. shown in figure 5 is an equivalent output circuit for dac a. the circuit is shown with all digital inputs high. the leak- age current source is the combination of surface and junction leakages to the substrate. the 1/256 current source rep- resents the constant 1-bit current drain through the ladder term inating resistor. the situation is reversed with all digital inputs low, as shown in figure 6. the output capacitance is code dependent, and therefore, is modulated between the low and high values.
memory 8 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f igure 3. s implified d/a c ircuit of 8408 f igure 4. n-c hannel c urrent s teering s witch f igure 5. e quivalent dac c ircuit (aii d igital i nputs high)
memory 9 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f igure 6. e quivalent dac c ircuit (aii d igital i nputs low) digital section figure 7 shows the digital input/output structure for one bit. the digital wr, wr , and rd controls shown in the figure are internally generated from the external a/b, r/w , ds1 , and ds2 signals. the combination of these signals decide which dac is selected. the digital inputs are cmos inverters, designed such that ttl input levels (2.4 v and 0.8 v) are converted into cmos logic levels. when the digital input is in the region of 1.2 v to 1.8 v, the input stages operate in their linear region and draw current from the +5 v supply (see typical supply current vs. logic level curve on page 6). it is recommended that the digital input voltages be as close to vdd and dgnd as is practical in order to minimize supply currents. this allows maximum savings in power di ssipation inherent with cmos devices. the three-state readback digital output drivers (in the active mode) provide ttl-compatible digital outputs with a fan-out of one ttl load. the three state digital readback leakage-current is typically 5 na. f igure 7. d igital i nput /o utput s tructure
memory 10 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 nterface logic section dac operating modes ? all dacs in hold mode. ? dac a, b, c, or d individually selected (write mode). ? dac a, b, c, or d individually selected (read mode). ? dacs a and c simultaneously selected (write mode). ? dacs b and d simultaneously selected (write mode). dac selection: control inputs, ds1 , ds2 , and a/b select which dac can accept data from the input port (see mode selection table). mode selection: control inputs ds and r/w control the operating mode of the selected dac. write mode: when the control inputs ds and r/w are both low, the selected dac is in the write mode. the input data latches of the selected dac are transparent, and its analog output responds to activity on the data inputs db0?db7. hold mode: the selected dac latch retains the data that was present on the bus line just prior to ds or r/w going to a high state. all analog outputs remain at the values corresponding to the data in their respective latches. read mode: when ds is low and r/w is high, the selected dac is in the read mode, and the data held in the appro- priate latch is put back onto the data bus.
memory 11 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 t able 4. mode selection table basic applications some basic circuit configurations are shown in figures 8 and 9. figure 8 shows the 8408 connected in a unipolar con- figuration (2-quadrant multiplication), and table 5 shows the code table. resistors r1, r2, r3, and r4 are used to trim full scale output. full-scale output voltage = vref ?1 lsb = vref (1?2?8) or vref x (255/256) with all digital inputs high. low temperature coefficient (approximately 50 ppm/c) resistors or trimmers should be selected if used. full scale can also be adjusted using vref voltage. this will eliminate resistors r1, r2, r3, and r4. in many applica- tions, r1 through r4 are not required, and the ma ximum gain error will then be that of the dac. each dac exhibits a variable output resistance that is code dependent.this produces a code-dependent, differential nonlinearity term at the amplifier?s output which can have a maximum value of 0.67 times the amplifier?s offset voltage. this differential nonlinearity term adds to the r-2r resistor ladder differential-nonlinearity; the output may no longer be monotonic. to maintain monotonicity and minimize gain and linearity errors, it is recommended that the op amp offset voltage be adjusted to less than 10% of 1 lsb (1 lsb = 2? 8 x vref or 1/256 x vref), or less than 3.9 mv over the operating temperature range. zeroscale output voltage (with all digital inputs low) may be adjusted using the op amp offset adjustment. capacitors c1, c2, c3, and c4 provide phase compensation and help prevent overshoot and ring- ing when using high speed op amps. figure 9 shows the recommended circuit configuration for the bipolar operation (4-quadrant multiplication), and table 6 shows the code table. trimmer resistors r17, r18, r19, and r20 are used only if gain error adjustments are required and range between 50 ? and 1000 ? . resistors r21, r22, r23, and r24 will range between 50 ? and 500 ? . if these resistors are used, it is essential that resistor pairs r9?r13, r10?r14, r11?r15, r12?r16 are matched both in value and tempco. they should be within 0.01%; wire wound or metal foil types are preferred for best temper- ature coefficient matching. the circuits of figure 8 and 9 can either be used as a fixed reference d/a converter, or as an attenuator with an ac input voltage.
memory 12 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 t able 5. u nipolar b inary c ode t able (r efer to f igure 8) f igure 8. q uad dac u nipolar o peration (2-q uadrant m ultiplication )
memory 13 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f igure 9. q uad dac b ipolar o peration (4-q uadrant m ultiplication ) t able 6. b ipolar (o ffset b inary ) c ode t able (r efer to f igure 9)
memory 14 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 application hints general ground management: ac or transient voltages between agnd and dgnd can appear as noise at the 8408?s analog output. note that in figures 5 and 6, iout2a/iout2b and iout 2c/iout 2d are connected to agnd. there- fore, it is recommended that agnd and dgnd be tied together at th e 8408 socket. in systems where agnd and dgnd are tied together on the backplane, two diodes (1n914 or equivalent) should be connected in inverse parallel between agnd and dgnd. write enable timing: during the period when both ds and r/w are held low, the dac latches are transparent and the analog output responds directly to the digital data input. to prevent unwanted variations of the analog output, the r/w should not go low until the data bus is fully settled (data valid). single supply, voltage output operation the 8408 can be connected with a single +5 v supply to produce dac output voltages from 0 v to +1.5 v. in figure 10, the 8408 r-2r ladder is inverted from its normal connection. a +1.500 v reference is connected to the current out- put pin 4 (iout 1a), and the normal vref input pin become s the dac output. instead of a normal current output, the r-2r ladder outputs a voltage. the op-490, consisting of four precision low power op amps that can operate its inputs and outputs to zero volts, buffers the dac to produce a low impedance output voltage from 0 v to +1.5 v full-scale. table 7 shows the code table. with the supply and reference voltages as shown, better than 1/2 lsb differential and integral nonlinearity can be expected. to maintain this performance level, the +5 v supply must not drop below 4.75 v. similarly, the reference voltage must be no higher than 1.5 v. this is because th e cmos switches require a minimum level of bias in order to maintain the linearity performance. t able 7. s ingle s upply b inary c ode t able (r efer to f igure 10)
memory 15 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f igure 10. u nipolar s upply , v oltage o utput dac o peration f igure 11. a d igitally p rogrammable u niversal a ctive f ilter
memory 16 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 a digitally programmable active filter a powerful d/a converter application is a programmable active filter design as shown in figure 11. the design is based on the state-variable filter topology which offers st able and repeatable filter characteristics. dac b and dac d can be programmed in tandem with a single digital byte load which sets the center frequency of the filter. dac a sets the q of the filter. dac c sets the gain of the filter transfer function. the unique feature of this design is that varying the gain of filter does not affect the q of the filter. similarly, the reverse is also true. this makes the programmability of the filter extremely reliable and predictable. note that low-pass, high-pass, and bandpass outputs are available. this sophisticated function is achi eved in only two ic packages. the network analyzer photo shown in figure 12 superimposes five actual bandpass responses ranging from the low- est frequency of 75 hz (1 lsb on) to a full-scale frequency of 19.132 khz (all bits on), which is equivalent to a 256 to 1 dynamic range. the frequency is determined by fc = 1/2 rc where r is the ladder resistance (rin) of the 8408, and c is 1000 pf. note that from devi ce to device, the resistance rin varies . thus some tuning may be necessary. f igure 12. p rogrammable a ctive f ilter b and -p ass f requency r esponse all components used are available off-the-shelf. using low drif t thin-film resistors, the 8408 exhibits very stable perfor- mance over temperature. the wide bandwidth of the op-470 produces excellent high frequency and high q response. in addition, the op470?s low input offset voltage assures an unusually low dc offset at the filter output.
memory 17 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f igure 13. a d igitally p rogrammable , l ow -d istortion s inewave o scillator a low-distortion, programmable sinewave oscillator by varying the previous state-variable filter topology slightly, one can obtain a very low distortion sinewave oscillator with programmable frequency feature as shown in figure 13. again, dac b and dac d in tandem control the oscillat- ing frequency based on the relationship fc = 1/2 rc. positive feedback is a ccomplished via the 82.5 k ? and the 20 k ? potentiometer. the q of the oscillator is determined by the ratio of 10 k ? and 475 ? in series with the fet transis- tor, which acts as an automatic gain control variable resistor. the agc action maintains a very stable sinewave ampli- tude at any frequency. again, only two ics accomplish a very useful function. at the highest frequency setting, the harmonic distortion level measures 0.016%. as the frequencies drop, distortion also drops to a low of 0.006%. at the lowest frequency setting, distortion came back up to a worst case of 0.035%
memory 18 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 f28-02 note: all dimensions in inches 28 p in r ad -p ak ? f lat p ackage s ymbol d imension m in n om m ax a 0.190 0.207 0.224 b 0.015 0.017 0.022 c 0.004 0.005 0.009 d -- 0.720 0.740 e 0.380 0.410 0.420 e1 -- -- 0.440 e2 0.180 0.250 -- e3 0.030 0.080 -- e 0.050 bsc l 0.360 0.370 0.380 q 0.062 0.073 0.081 s1 0.000 0.027 -- n28
memory 19 all data sheets are subject to change without notice ?2002 maxwell technologies all rights reserved. quad 8-bit multiplying cmos d/a converter with memory 8408 08.20.02 rev 1 important notice: these data sheets are created using the chip manufacturer s published specifications. maxwell technologies verifies functionality by testing key parameters either by 100% testing, sample test ing or characterization. the specifications presented within these data sheets represent the latest and most accurate information available to date. however, these specifications are subject to change without notice and maxwell technologies assumes no responsibility for the us e of this information. maxwell technologies? products are not authorized for use as critical components in li fe support devices or systems without express written approval from maxwell technologies. any claim against maxwell technologies must be made within 90 days from the date of shipment from maxwell tech- nologies. maxwell technologies? liability shall be limited to replacement of defective parts.

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